1. Field of the Invention
The present disclosure generally relates to the fabrication of semiconductor devices, and, more particularly, to a method for forming an air gap structure using carbon-containing spacer.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. In integrated circuits fabricated using metal-oxide-semiconductor (MOS) technology, field effect transistors (FETs) (both NMOS and PMOS transistors) are provided that are typically operated in a switching mode. That is, these transistor devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). FETs may take a variety of forms and configurations. For example, among other configurations, FETs may be either so-called planar FET devices or three-dimensional (3D) devices, such as finFET devices.
A field effect transistor (FET), irrespective of whether an NMOS transistor or a PMOS transistor is considered, and irrespective of whether it is a planar or 3D finFET device, typically comprises doped source/drain regions that are formed in a semiconductor substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. The gate insulation layer and the gate electrode may sometimes be referred to as the gate structure for the device. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region. To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
The switching speed of a FET is affected not only by the channel length, but also by the materials employed, which affect the capacitance of the device. One technique for decreasing the device capacitance is to employ dielectric materials with reduced dielectric constants or so-called “low-k” materials. For this reason, it has been proposed to introduce “air gaps,” at least in critical device areas, since air or similar gases may have a dielectric constant of approximately 1.0. One technique for forming air gaps involves forming nitride spacers on the sidewalls of a transistor gate structure, forming an interlayer dielectric layer above the gate electrode and planarizing it to expose the spacers. The spacers are removed using a selective etch process, leaving an air gap proximate the gate structure in the space that had been occupied by the spacer.
This process has several limitations as it requires the selective etching of the spacer material. As more exotic materials are used in the formation of transistor devices to improve performance, it becomes difficult to selectively etch the spacer material without damaging some other part of the transistor device. For example, silicon nitride is conventionally used for the spacer material, as it may be etched selectively to other dielectric materials in the device, such as silicon dioxide based dielectrics. Silicon nitride may also be used to protect the source/drain regions of the transistor device during the process flow. For example, the source/drain regions of a P-type transistor device may be provided with one type of epitaxial semiconductor material, while the source/drain regions of an N-type transistor device may be provided with a different type of epitaxial semiconductor material. The N-type transistors may be covered with a silicon nitride protective layer while the epitaxial semiconductor material is formed for the P-type devices, and vice versa. The selective etching of the spacers to provide air gaps can also remove the silicon nitride material protecting the source/drain regions, causing damage thereto.
Moreover, the planarization process to expose the spacers may also expose the gate structure or a protective cap layer (e.g., silicon nitride) formed thereabove. The selective spacer etch can also damage the gate structure or its cap layer, reducing performance or introducing defects.
The present disclosure is directed to various methods and resulting devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.